DARPA Initiates Low Temperature Integrated Circuits Project to Get Over Moore's Law Limitations

The U.S. Defense Advanced Research Projects Agency (DARPA) has initiated a program to develop very low temperature device technology for defense applications, to overcome power efficiency limitations in high-performance computing currently guided by Moore’s law.

Moore's law states that the number of transistors on a computer chip that will double about every 18–24 months is slowing due to a host of technical challenges, including operating voltage reduction, making it difficult to continue with this paradigm.

“Today, we’re aggressively reaching the end of Moore’s Law scaling and are faced with the inability to scale power density much further in order to improve computing performance,” said Jason Woo, a program manager in DARPA’s Microsystems Technology Office (MTO). “A viable solution is cold computing. While microelectronics is typically designed to operate at room temperature, we know that device characteristics improve significantly at reduced temperatures. Very low temperature devices – those operating at 77K or below – have the potential to overcome the power scaling limit, but challenges exist when you apply them to very large scale integration.”

To overcome the barriers to thermal and power density scaling in HPC systems, DARPA developed the Low Temperature Logic Technology (LTLT) program. LTLT seeks to enable a dramatic improvement in performance over power when operating electronics at temperatures close to that of liquid nitrogen (~77K or -321F). The goal of LTLT is to develop high-performance, low-temperature 14nm node or below complementary metal-oxide-semiconductor (CMOS) FinFETs by making modifications to advanced very large scaled integration (VLSI) processes. The resulting device/circuit technology should be capable of achieving a 25X improvement in performance/power compared to state-of-the-art (SOA) central processing units (CPUs) operating at room temperature. LTLT also seeks to develop and demonstrate a compact static random-access memory (SRAM) cell that can operate at 77K to complete the basic circuit elements needed for HPC engines.

To achieve the program’s objectives, LTLT aims to exploit the unique device/material characteristics and performance of today’s advanced nodes FinFETs operating at very low temperatures to develop transistors and memory cells with superior performance/power than is realizable by simply cooling current SOA VLSI technologies. The program is broken out into two separate research areas. The first will focus on researching, developing, and delivering a fabrication technology for highly integrated, advanced node CMOS operating at 77K, with low supply voltage and high performance. The target technology will be able to integrate low temperature transistors, SRAM cells with 25X lower switching energy at 77K, and a supporting circuit/system design.

The second area in the program will explore advanced research concepts focused on high-risk/high payoff FinFET VLSI-compatible solutions for individual technical challenges at 77K. Three specific challenges will be explored, which include ultra-low power, high-speed scaled transistors with new switching or transport mechanisms; compact, high speed, low energy SRAM cells; and new circuit techniques that utilize novel LTLT transistors and memory cells to achieve a 45X performance/power improvement.

The LTLT program will also utilize the benefits of DARPA’s recently unveiled Toolbox Initiative. The DARPA Toolbox provides open licensing opportunities with commercial technology vendors to the researchers behind the Agency’s programs. Through this initiative, DARPA researchers – or performers – are provided easy, low-cost, scalable access to state-of-the-art tools and intellectual property (IP) under predictable legal terms and streamlined acquisition procedures.